Method of estimating wiring complexity degree in semiconductor integrated circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsFumihito Watanuki, Eiji Nagata
Life of this patent
Estimating the term…
Abstract
A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.
Claims11
A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, comprising the steps of:
- predicting a power-supply wiring space used in the semiconductor integrated circuit;
- dividing the predicted power-supply wiring space onto respective wiring layers;
- and
- estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.
Dependencies are inferred from the claim text.