Test point insertion method

A test point insertion method, comprising the steps of:

• (a) inserting a test point to enable fault detection in a circuit which is disabled by propagation of a fixed value of a scan mode signal in scan design of a semiconductor integrated circuit;
• (b) placing cells after step (a);
• and
• (c) consolidating consolidatable test points after step (b).

A test point insertion method, comprising the steps of:

• (a) determining a node for insertion of a test point which enables fault detection in a circuit disabled by propagation of a fixed value of a scan mode signal in scan design of a semiconductor integrated circuit;
• (b) placing cells after step (a);
• (c) placing test points in a distributed fashion in an area where a congestion degree of the cells placed at step (b) and lines is lower than a predetermined reference value;
• and
• (d) connecting the node determined for test point insertion at step (a) and the test point placed at step (c).

A test point insertion method, comprising the steps of:

• (a) determining a node for insertion of a test point which enables fault detection in a circuit disabled by propagation of a fixed value of a scan mode signal in scan design of a semiconductor integrated circuit, the determined node including a node to which a control test point is to be inserted;
• (b) inserting, to the node to which a control test point is to be inserted, a logic circuit which is necessary for insertion of a control test point;
• (c) placing cells after step (b);
• (d) placing test points in a distributed fashion in an area where a congestion degree of the cells placed at step (c) and lines is lower than a predetermined reference value;
• and
• (e) connecting the control test point placed at step (d) to a terminal of the logic circuit inserted at step (b).

A test point insertion method, comprising the steps of:

• (a) inserting a test point to enable fault detection in a circuit which is disabled by propagation of a fixed value of a scan mode signal in scan design of a semiconductor integrated circuit;
• (b) placing cells after step (a);
• and
• (c) if necessity of changing circuit specifications or modifying the circuit occurs after step (b), modifying the circuit using a test point as a repair cell.