Information processing apparatus

A stream processor for performing a plurality of processes parallel to each other on data read from a memory, comprising:

• a means for reading data to be processed from said memory according to an input address information contained in a plurality of descriptors, processing said data by predetermined process, and storing the processed data back into said memory according to an output address information contained in each of said plurality of descriptors, wherein each of said plurality of descriptors includes said input address information and said output address information, and wherein said stream processor can process a plurality of said predetermined processes parallel to each other.

A program for controlling an information processing apparatus having a memory for storing a plurality of descriptors, wherein each of said plurality of descriptors contains input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data, a stream processor for performing a plurality of processes parallel to each other by acquiring said plurality of descriptors from said memory, reading data to be processed from said memory according to said input address information contained in each of said plurality of descriptors, processing said data by predetermined process, and storing the processed data back into said memory according to the output address information contained in each of said plurality of descriptors, said stream processor can process a plurality of said predetermined processes parallel to each other, and a host processor for controlling operation of said stream processor, said program being executable by said host processor and comprising the steps of:

• generating a plurality of descriptors which are successively readable by said stream processor;
• and
• storing said plurality of descriptors in said memory.