Semiconductor device

A semiconductor device comprising:

• a first power supply line connected to a first power supply terminal to which a first power supply voltage is supplied;
• a second power supply line connected to a second power supply terminal to which a first reference voltage is supplied;
• a third power supply line connected to a third power supply terminal to which a second power supply voltage is supplied;
• a fourth power supply line connected to a forth power supply terminal to which a second reference voltage is supplied;
• a first circuit block connected to the first power supply line and the second power supply line;
• a second circuit block connected to the third power supply line and the fourth power supply line;
• and
• signal lines connecting the first circuit block and the second circuit block,
• wherein an I/O area including the first, the second, the third, and the fourth power supply terminals and plural input/output buffers is arranged on the outer periphery of the semiconductor device, and
• wherein a core area including the first circuit block and the second circuit block is arranged in an area inside the I/O area,
• the core area comprising:
• a first clamp circuit connected between the first power supply line and the fourth power supply line;
• a second clamp circuit connected between the second power supply line and the third power supply line;
• and
• a third clamp circuit connected between the second power supply line and the fourth power supply line.

A semiconductor device including a first circuit block that operates with a first power supply voltage and a first reference voltage, and plural circuit blocks that each operate with power supply voltages and reference voltages supplied from power supply systems different from the power supply system that supplies the first power supply voltage and the first reference voltage, and each perform transmission and reception of signals with the first circuit block,

• the semiconductor device comprising:
• first plural circuits that clamp potentials between the first power supply voltage and reference voltages each supplied to the plural circuit blocks;
• second plural circuits that clamp potentials between the first reference voltage and power supply voltages each supplied to the plural circuit blocks;
• and
• third plural circuits that clamp potentials between the first reference voltage and reference voltages each supplied to the plural circuit blocks.