Non-volatile memory and method of fabricating same

A semiconductor device comprising:

• an insulated floating gate overlying a semiconductor substrate, the floating gate has a side surface and a top surface;
• an insulated program gate formed at least on the side surface of the floating gate;
• an erase insulated gate disposed adjacent the floating gate;
• a first dielectric layer disposed between the insulated floating gate and the insulated program gate;
• a second dielectric layer disposed between the insulated floating gate and the insulated erase gate, wherein a capacitive coupling ratio between the floating gate and the program gate is greater than a capacitive coupling ratio between the program gate and the erase gate;
• and
• first and second junction regions disposed along opposite sides of the insulated floating gate.

A non-volatile memory comprising:

• an insulated first gate disposed on a semiconductor substrate and having a first height;
• an insulated second gate that partially overlaps the first gate and that has a second height that is greater than the first height;
• and
• an insulated third gate that partially overlaps the first gate and that has a third height that is greater than the second height.

A system comprising:

• a non-volatile memory comprising:
• an insulated floating gate overlying a semiconductor substrate, the floating gate has a side surface and a top surface;
• an insulated program gate formed at least on the side surface of the floating gate;
• an erase insulated gate disposed adjacent the floating gate;
• a first dielectric layer disposed between the insulated floating gate and the insulated program gate;
• a second dielectric layer disposed between the insulated floating gate and the insulated erase gate, wherein a capacitive coupling ratio between the floating gate and the program gate is greater than a capacitive coupling ratio between the program gate and the erase gate;
• and
• first and second junction regions disposed along opposite sides of the insulated floating gate;
• and
• a central processing unit (CPU) in electrical communication with the non-volatile memory.

A method comprising:

• depositing a gate dielectric layer on a semiconductor substrate;
• forming a first conductive layer on the gate dielectric layer;
• patterning the first conductive layer disposed on the gate dielectric layer to form a floating gate;
• depositing a first dielectric layer having a first thickness on the floating gate;
• forming a second conductive layer on the gate dielectric layer and the first dielectric layer;
• patterning a second conductive layer to form a program gate that partially overlaps the floating gate;
• depositing a second dielectric layer having a second thickness on the program gate, the first dielectric layer, and the gate dielectric layer;
• forming a third conductive layer on the second dielectric layer;
• and
• patterning a third conductive layer disposed to form an erase gate that partially overlaps the program gate and the floating gate.

A method comprising:

• depositing a gate dielectric layer on a semiconductor substrate;
• patterning a first conductive layer disposed on the gate dielectric layer to form a floating gate;
• depositing a first mask layer on the gate dielectric layer and the floating gate;
• patterning the first mask layer to form a first mask pattern that partially exposes the floating gate;
• implanting ions in a top surface of the floating gate using the first mask pattern as a mask;
• removing the first mask pattern;
• depositing a second mask layer on the gate dielectric layer and the floating gate;
• patterning the second mask layer to form a second mask pattern that exposes the floating gate;
• thermally oxidizing the top surface of the floating gate;
• depositing a first dielectric layer having a first thickness on the floating gate;
• patterning a second conductive layer disposed on the gate dielectric layer and the first dielectric layer to form a program gate that partially overlaps the floating gate;
• depositing a second dielectric layer having a second thickness on the program gate, the first dielectric layer, and the gate dielectric layer;
• and
• patterning a third conductive layer disposed on the second dielectric layer to form an erase gate that partially overlaps the program gate and the floating gate.