Semiconductor device having polycide wiring layer, and manufacturing method of the same

A semiconductor device comprising:

• a semiconductor substrate having element isolation regions and an element region surrounded by the element isolation regions;
• and
• a first transistor and a second transistor which are formed in the element region of the semiconductor substrate,
• each of the first and second transistors comprising:
• a gate insulation film formed on the semiconductor substrate;
• a gate electrode formed on the gate insulation film and including a polysilicon layer and a silicide layer on the polysilicon layer;
• a spacer formed on a side wall of the gate electrode;
• and
• impurity diffusion layers separately formed in the semiconductor substrate and surrounding the gate electrode,
• the spacer of the first transistor being lower in level than the spacer of the second transistor, and
• the silicide layer of the gate electrode of the first transistor being thicker than the silicide layer of the gate electrode of the second transistor.

A semiconductor device manufacturing method comprising:

• forming element-isolating insulation films in element isolation regions of a semiconductor substrate;
• continuously forming a polysilicon layer on the semiconductor substrate such that the polysilicon layer is formed on the element-isolating insulation films and on an element region surrounded by the element-isolating insulation films;
• introducing impurities into the element region of the semiconductor substrate, using the polysilicon layer as a mask;
• forming a spacer which is in contact with a side wall of the polysilicon layer;
• forming a mask layer having an opening in which the spacer in each of the element isolation regions is exposed;
• etching the spacer, using the mask layer as a mask, such that shoulder portions which are near the spacer in each of the element isolation regions and the polysilicon layer in each of the element isolation regions are exposed;
• forming a silicide layer on the polysilicon layer by a salicide process and permitting a silicide layer to grow on the exposed shoulder portions of the polysilicon layer such that the silicide layer is thicker in each element isolation region than in the element region.