PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same

A phase-change random access memory (PRAM) having a circuit wire in a peripheral circuit region, comprising:

• a first semiconductor substrate defining at least one reference active region;
• at least one other semiconductor substrate located in sequence on a vertical line passing a main surface of the reference active region, defining at least one other active region, respectively, and being in parallel with the first semiconductor substrate;
• a lower peripheral gate pattern located on the first semiconductor substrate of the reference active region and upper peripheral gate patterns located respectively on the other semiconductor substrates of the other active regions;
• metal node plugs located at both sides of the lower and upper peripheral gate patterns and being in contact with the first semiconductor substrate penetrating the other semiconductor substrates,
• wherein one of the metal node plugs is located below the circuit wire and is electrically connected to the circuit wire.

A method of forming a PRAM having a phase change layer pattern in a cell array region, comprising:

• forming a lower cell gate pattern on a first semiconductor substrate of at least one reference active region;
• forming a pad interlayer insulating layer on the first semiconductor substrate to cover the lower cell gate pattern;
• forming upper cell gate patterns on at least one other semiconductor substrate of at least one other active region which are formed vertically in sequence from the upper surface of the pad interlayer insulating layer above the reference active region;
• forming pad interlayer insulating layers on the other semiconductor substrates to cover the upper cell gate patterns;
• and
• forming metal node plugs at both sides of the lower and upper cell gate patterns to be in contact with the first semiconductor substrate penetrating the pad interlayer insulating layers and the other semiconductor substrates,
• wherein the other active regions are formed in parallel with the reference active region, and the phase change layer pattern is formed above the metal node plugs and is electrically connected to one of the metal node plugs.

A method of forming a PRAM having a circuit wire in a peripheral array region, comprising:

• forming a lower peripheral gate pattern on a first semiconductor substrate of at least one reference active region;
• forming a pad interlayer insulating layer on the first semiconductor substrate to cover the lower peripheral gate pattern;
• forming upper peripheral gate patterns on at least one other semiconductor substrate of at least one other active region, which are formed vertically in sequence from the upper surface of the pad interlayer insulating layer above the reference active region;
• forming pad interlayer insulating layers on the other semiconductor substrates to cover the upper peripheral gate patterns;
• and
• forming metal node plugs at both sides of the lower and upper peripheral gate patterns to be in contact with the first semiconductor substrate penetrating the pad interlayer insulating layers and the other semiconductor substrates,
• wherein the other active regions are formed in parallel with the reference active region, and the circuit wire is formed above the metal node plugs and is electrically connected to one of the metal node plugs.