One-hot encoded instruction register for boundary scan test compliant devices

A method of Boundary Scan testing at least a part of the circuitry of an integrated circuit chip, wherein the integrated circuit chip is operated in one of a plurality of Boundary Scan test modes to test the at least part of the circuitry, the method comprising:

• storing a one-hot encoded instruction identifying said one of the Boundary Scan test modes in an instruction register of the integrated circuit chip;
• performing, by a Boundary Scan register, a test on the tested part of the circuitry by applying a test signal to the tested part of the circuitry and/or storing an output of the tested part of the circuitry in accordance with said one of the Boundary Scan test modes;
• and
• extracting, by the Boundary Scan register, which test to perform on the tested part of the circuitry from the one-hot encoded instruction stored in the instruction register.

A hardware device arranged to perform a Boundary Scan test on at least part of its circuitry and comprising an integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry comprised in the integrated circuit chip is tested;

• and
• wherein the integrated circuit chip comprises:
• a Boundary Scan register arranged to perform a test on the tested part of the circuitry by applying a test signal to the tested part of the circuitry and/or storing an output of the tested part of the circuitry in accordance with one of the Boundary Scan test modes;
• and
• an instruction register arranged to store a one-hot encoded instruction identifying one of the Boundary Scan test modes;
• wherein the Boundary Scan register is further arranged to extract which test to perform on the tested part of the circuitry from the one-hot encoded instruction stored in the instruction register.