Method and apparatus for deferred decision signal quality analysis

Abstract

A signal analysis circuit includes a sampling circuit operative to sample the characteristics of an input signal at various points within a bit window in response to a sample clock signal. A sampling control circuit is coupled to the sampling circuit and is operative to provide the sample clock signal in response to a sample control signal. The sample clock signal provides a variable time function such that the input signal characteristics may be sampled at several times during the input signal or bit window period. A control circuit is coupled to the sampling circuit and the sampling control circuit, and is operative to provide the sample control signal in response to the number of times the input signal is within a signal characteristic of interest. In an exemplary embodiment, the characteristic of interest is a reference pattern that may be synchronized with the input data signal. The reference pattern is provided a pattern generation circuit that is resident within a larger comparison and counting circuit.

Dependencies are inferred from the claim text.