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US 2006/0069953 A1Published application
Debug in a multicore architecture
AssigneesSynopsys, Inc., Fujitsu Semiconductor Limited
InventorsMark Lippett, Ayewin Oung
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AssigneesSynopsys, Inc., Fujitsu Semiconductor Limited
InventorsMark Lippett, Ayewin Oung
Estimating the term…
According to a first aspect of the present invention, there is provided a method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators indicative of one or more parameters relating to the function and/or identity of a thread or threads comparing at least some of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.
A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising:
A thread level debug controller for software debug in a multicore processor architecture having a plurality of interconnected processor elements, each element providing resources for processing threads, the debug controller being in communication with each of the said processor elements and comprising monitor logic for monitoring the allocation and execution of threads within the multicore processor architecture.
Dependencies are inferred from the claim text.