Embedded system with reduced susceptibility to single event upset effects

An method of making an embedded system with reduced susceptibility to single event upset effects, the method comprising:

• (a) providing an instruction memory configured to store at least one instruction set, the instruction memory utilizing a parity checking error-detection scheme;
• (b) providing a non-volatile memory configured to store a copy of the at least one instruction set;
• (c) providing a data memory configured to store at least one data sequence, the data memory utilizing an error correction coding scheme;
• and
• (d) providing a controller responsive to the instruction memory, the non-volatile memory, and the data memory, the controller configured to replace the at least one instruction set in the instruction memory with the copy of the at least one instruction set from the non-volatile memory if at least one parity error is detected in connection with the at least one instruction set in the instruction memory, the controller further configured to operate in conjunction with the data memory to implement the error correction coding scheme.