Back to results
US 2006/0069936 A1Published application
Global and pseudo power state management for multiple processing elements
AssigneeIntel Corporation
InventorsBernard Lint, Todd Dutton, Kushagra Vaid
Life of this patent
Estimating the term…
Abstract
A method and apparatus for global and local power management is herein described. Hardware within monitor/receives power management requests for any number of processing elements and adjusts global performance resources to change the global power state of all the processing elements or adjusts a local performance resource for a processing element to operate that processing element at a pseudo power state within the global power state.
Claims42
An apparatus comprising:
- a first processing element and a second processing element capable of receiving independent power management requests;
- and
- a power module associated with the first and second processing elements to monitor said independent power management requests and to adjust performance resources of said first and second processing elements based on said independent power management requests.
An integrated circuit comprising:
- a microprocessor comprising a first thread operable to receive a first power management request and a second thread operable to receive a second power management request;
- and
- a power module associated with the microprocessor operable to adjust the performance of at least the second thread based on at least the first and second power management request.
An apparatus comprising:
- a microprocessor comprising a plurality of logical processors, wherein the plurality of logical processors are capable of operating in a plurality of global power states and at least one pseudo-power state within each global power state;
- and
- a circuit capable of receiving a power management request for independently changing the global power state of a first logical processor of the plurality of logical processors, wherein the circuit is operable to (1) change the pseudo-power state of the first logical processor, if the requested global power state change would not result in all of the plurality of logical processors operating at the same global power state;
- and (2) change the global power state of the plurality of logical processors if the requested global power state change would result in all of the plurality of logical processors operating at the same global power state.
1 more element
A method comprising:
- receiving a first power management request from an operating system for a first thread;
- receiving a second power management request from the operating system for a second thread;
- adjusting at least one performance resource based on the first power management request and the second power management request.
A method comprising:
- receiving a power command for a first processing element, wherein the power command requests the first processing element to operate at a first power state;
- checking a previous power command for a second processing element coupled to the first processing element;
- (1) changing a first local performance resource to operate the first processing element at a first pseudo-power state, if the previous power command for the second processing element requested the second processing element to operate at a higher performance power state than the first power state;
- and
- (2) changing a first global performance resource to operate the first and the second processing elements at the first power state, if the previous power command for the second processing element requested the second processing element to operate at the first power state.
2 more elements
A system comprising:
- a storage medium for storing an operating system (OS) code, wherein the OS code includes a plurality of power commands;
- a host processor coupled to the storage medium comprising a plurality of logical processors to execute the plurality of power commands, each power command capable of independently requesting a power state change in one of the plurality of logical processors, and a power module to adjust performance resources of the plurality of logical processors based on a currently executed power command and at least one previously executed power command.
Dependencies are inferred from the claim text.