Methods of forming self-aligned floating gates using multi-etching

A method of forming a floating gate of a non-volatile memory device comprising:

• implanting impurities into adjacent field isolation regions on a substrate to increase an etch rate of the adjacent field isolation regions without the implanted impurities;
• etching a mask pattern between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form an opening having a width defined by a side wall of the adjacent field isolation regions above the surface;
• and then
• etching the side wall of the adjacent field isolation regions to increase the width of the opening.

A method of manufacturing a semiconductor device, comprising:

• forming a mask pattern on a substrate, the mask pattern including a first opening through which a first portion of the substrate is exposed;
• forming a trench by etching the first portion of the substrate;
• forming an isolation pattern filling up the first opening and the trench;
• forming a second opening by etching an upper portion of the mask pattern, so that the second opening is defined by the upper portion of the isolation pattern and a recessed mask pattern;
• partially removing the upper portion of the isolation pattern defining the second opening to thereby increase a size of the second opening;
• forming a third opening by etching the recessed mask pattern, a second portion of the substrate being exposed through the third opening;
• and
• forming a conductive layer on the second portion of the substrate and the isolation pattern to a thickness to fill up the second and the third openings.