Isolation trench perimeter implant for threshold voltage control

A method of forming isolation trenches in a semiconductor fabrication process, comprising:

• forming a patterned masking structure overlying a substrate to expose a first area of the substrate;
• forming spacers on sidewalls of the patterned masking structure, wherein the spacers cover a perimeter region of the first area thereby leaving a second area, smaller than the first area, exposed;
• etching the second exposed area to form an isolation trench and filling the trench with a trench dielectric:
• removing the spacers to expose the perimeter region;
• using the masking structure and the trench dielectric as a mask, implanting an impurity into a portion of the substrate underlying the exposed perimeter region, wherein the implanted impurity surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate;
• prior to depositing the first and second masking layers, depositing a pad layer overlying the substrate, wherein the first cad layer comprises an oxide;
• and
• following deposition of the pad layer and prior to forming the patterned masking structure, depositing a polish stop layer overlying the pad layer.

A semiconductor fabrication process, comprising:

• forming an isolation trench in a semiconductor substrate;
• filling the trench with an isolation dielectric;
• forming an impurity distribution below all upper surface of a semiconductor substrate, wherein the impurity distribution is confined to a perimeter region surrounding the isolation trench and wherein a conductivity type of the implanted species and a conductivity type of a substrate well in which the isolation trench resides are the same;
• and
• forming a silicon nitride polish stop layer overlying the pad oxide layer and underlying the polysilicon layer
• wherein forming the isolation trench includes:
• exposing a first area of the substrate, wherein the first area includes a second area into which the isolation trench is formed and the perimeter region surrounding the isolation trench;
• masking the perimeter region surrounding the second area thereby leaving the second area exposed;
• and
• etching the exposed second area;
• wherein exposing the first area of the substrate comprise forming a patterned masking structure overlying a pad oxide layer overlying the substrate, wherein the patterned masking structure is patterned to expose the first area of the substrate;
• wherein forming the patterned masking structure comprises depositing a first masking layer overlying the pad oxide layer and depositing a second masking layer overlying the first masking layer;
• and
• wherein the first masking layer is polycrystalline silicon (polysilicon) and wherein the second masking layer is silicon nitride.

A semiconductor fabrication process, comprising:

• forming an isolation trench in a semiconductor substrate;
• filling the trench with an isolation dielectric;
• forming, an impurity distribution below an upper surface of a semiconductor substrate, wherein the impurity distribution is confined to a perimeter region surrounding the isolation trench and wherein a conductivity type of the implanted species and a conductivity type of a substrate well in which the isolation trench resides are the same;
• and
• forming a gate dielectric overlying the substrate and a gate electrode overlying the gate dielectric to form a transistor, wherein exterior portions of the gate electrode overlie the impurity distribution, and wherein a conductivity type of the impurity distribution adjusts the threshold voltage at the exterior portions of the gate electrode.