Timing circuit for data packet receiver
AssigneeLucent Technologies Inc.
InventorMarcus Duelk
Life of this patent
Estimating the term…
Abstract
A timing circuit for a receiver adapted for receiving data packet transmissions, each packet having a particular data frequency, the timing circuit comprising: (a) a clock generating circuit for generating a clock signal derived from a local reference clock signal and not from received data packets; and (b) a phase shifter circuit for synchronizing the phase of the clock signal to that of the particular data frequency
Claims25
A timing circuit for a receiver adapted for receiving data packet transmissions having a particular data frequency, said timing circuit comprising:
- a clock generating circuit for generating a clock signal derived from a local reference clock signal and not from received data packets;
- and
- a phase shifter circuit for synchronizing the phase of said clock signal to that of said particular data frequency.
A receiver adapted for receiving data packet transmissions, each packet having a particular data frequency, said receiver comprising:
- a timing circuit comprising at least a clock generating circuit for generating a clock signal derived from a local reference clock signal and not from received data packets;
- and
- a phase shifter circuit for synchronizing the phase of said clock signal to that of said particular data frequency.
A method of receiving data packets, each data packet having a particular data frequency, said method comprising:
- generating a clock signal based on a local reference clock signal and not from said particular data frequency;
- and
- shifting said phase position of said clock signal to synchronize the phase of the clock signal with that of said particular data frequency.
Dependencies are inferred from the claim text.