Semiconductor memory device and method for testing same

A semiconductor memory device comprising:

• a memory cell array composed of a plurality of memory cells whose addresses are represented by a plurality of row addresses and a plurality of column addresses;
• a row selecting unit which selects the memory cells at the specified rows from among the memory cells;
• a column selecting unit which selects the memory cells at the specified columns from among the memory cells;
• a data writing unit which writes data into the specified memory cells selected by the row selecting unit and the column selecting unit;
• a data reading unit which reads the data from the specified memory cells;
• and
• a specified row forcefully controlling unit, the specified row forcefully controlling unit forcefully making the control of the memory cells selected by using a specified row address signal to the control exercised during operation different from normal operation.

A semiconductor memory device comprising:

• a memory cell array composed of a plurality of memory cells whose addresses are represented by a plurality of row addresses and a plurality of column addresses;
• a row selecting unit which selects the memory cells at the specified rows from among the memory cells;
• a column selecting unit which selects the memory cells at the specified columns from among the memory cells;
• a data writing unit which writes data into the specified memory cells selected by the row selecting unit and the column selecting unit;
• a data reading unit which reads the data from the specified memory cells;
• and
• a specified column forcefully controlling unit, the specified column forcefully controlling unit forcefully making the control of the memory cells selected by using a specified column address signal the control exercised during operation different from normal operation.