Apparatus and method for a one-phase write to a one-transistor memory cell array

A memory, comprising:

• a memory cell array including a plurality of memory cells arranged in rows and columns;
• a plurality of wordlines, each connected to a corresponding one of the rows of the memory cell arrays;
• a plurality of bitlines, each bitline connected to a corresponding one of the columns of the memory cells;
• and
• an input/output (I/O) circuit to store a logic 0 value within at least one memory cell of a selected wordline and to store a logic 1 value within at least one memory cell of the selected wordline during a one-phase write cycle to the selected wordline of the memory cell array.

A system comprising:

• an embedded processor;
• and
• an embedded memory coupled to the embedded processor, the embedded memory comprising:
• a memory cell array including a plurality of memory cells arranged in rows and columns,
• a plurality of wordlines, each connected to a corresponding one of the rows of the memory cell arrays,
• a plurality of bitlines, each bitline connected to a corresponding one of the columns of the memory cells, and
• an input/output (I/O) circuit to store a logic 0 value within at least one memory cell of a selected wordline and to store a logic 1 value within at least one memory cell of the selected wordline during a one-phase write cycle to the selected wordline of the memory cell array.