Integrated memory circuit arrangement
AssigneeInfineon Technologies AG
InventorGeorg Tempel
Life of this patent
Estimating the term…
Abstract
A memory circuit arrangement includes a switching element per column that can be used to connect or disconnect two bit lines for memory cells of a column. The switching element leads to a reduction of the chip area and/or to an improvement in the electronic properties of the memory circuit arrangement.
Claims20
An integrated memory circuit arrangement comprising:
- a plurality of memory cells arranged in a matrix where the memory cells are arranged in of rows and columms, each memory cell including at least one transistor;
- word lines coupled to control electrodes of the transistors of memory cells of a row of the matrix;
- bit lines coupled to electrodes of the transistors of memory cells of a column of the matrix;
- at least one switching element per column enabling production and disconnection of an electrically conductive connection of two bit lines of a common column;
- and
- a collective line in the row direction of the matrix where at least one further switching element per column enables the production and disconnection of an electrically conductive connection of the collective line to a respective bit line, the collective line having the same potential in all of the operating modes.
An integrated memory circuit arrangement, comprising:
- a plurality of memory cells arranged in matrix-type fashion, the memory cells each containing at least one transistor;
- word lines at the control electrodes of the transistors of memory cells of a row of the matrix;
- bit lines at terminal electrodes of the transistors of memory cells of a column of the matrix;
- and
- a collective line in the row direction of the matrix, at least one switching element per column enabling the production and disconnection of an electrically conductive connection of the collective line to a respective bit line, where the collective line carries the same potential in all of the operating modes.
An electronic memory arrangement having memory cells arranged in rows and columns, the row being defined by word lines and the columns being defined by bit lines, the electronic memory arrangement comprising:
- bit line switching means for switching an electrical connection between two bit lines of a column of the memory arrangement.
- reference switching means for switching at least one bit line of a column to a reference potential, the reference potential being common for all of the operating modes of the memory circuit.
A method for controlling data in an electronic memory arrangement having memory cells arranged in rows and columns, the row being defined by word lines and the columns being defined by bit lines, the method comprising:
- switching an electrical connection between two bit lines of a column of the memory arrangement.
- switching at least one bit line of a column to a reference potential, the reference potential being common for all of the operating modes of the memory circuit.
Dependencies are inferred from the claim text.