Content addressable memory cell including resistive memory elements

A content addressable magnetic memory cell comprising:

• a first resistive magnetic memory element and a second resistive magnetic memory element being able to be brought into states exhibiting different resistance values and being coupled in a first series connection;
• a first transistor being a P-channel transistor and a second transistor being an N-channel transistor, the first and second transistors having drain-source-paths and gate electrodes, the drain-source-paths of the first and second transistors being connected in a second series connection and being connected to at least one of first current lines, said first current lines being precharged to a third potential value being smaller than said first potential value and being larger than said second potential value;
• and
• a second current line being connected to the second series connection of transistors between the first and second transistors.

A memory cell comprising:

• a voltage divider configured to provide a first voltage, the voltage divider including a first resistive memory element and a second resistive memory element, the first resistive memory element and the second resistive memory element configured to be set to different logic states,
• a first transistor configured to turn on in response to the first voltage exceeding a first value to provide a first signal;
• and
• a second transistor configured to turn on in response to the first voltage exceeding a second value greater than the first value to provide a second signal,
• wherein the first signal and the second signal indicate a logic state of the first resistive memory element and the second resistive memory element.

A method for sensing the state of a memory cell, the method comprising:

• dividing a first voltage between a first resistive memory element and a second resistive memory element to provide a second voltage, the first resistive memory element and the second resistive memory element configured to be set to different logic states;
• providing a first signal in response to the second voltage exceeding a first value;
• and
• providing a second signal in response to the second voltage exceeding a second value,
• wherein the first signal and the second signal indicate a logic state of the first resistive memory element and the second resistive memory element.