Flat display apparatus and driving method for flat display apparatus

A flat display apparatus for displaying an image having a pseudo gradation by varying the gradation of each pixel with a variation pattern different from that of an adjacent pixel in a unit of a frame, comprising:

• a display section having a plurality of pixels disposed in a matrix thereon;
• a vertical driving circuit for successively selecting said pixels of said display section in a unit of a line;
• a horizontal driving circuit for outputting a driving signal to said display section in response to the selection of the pixels by said vertical driving circuit;
• and
• a data processing circuit for processing image data and outputting resulting data to said horizontal driving circuit,
• said data processing circuit including:
• a signal pattern generation circuit for generating a signal pattern representative of the variation pattern;
• and
• a modulation circuit for adding, in response to a logic value of a lower order side bit or bits of the image data relating to display of the pseudo gradation, a logic value of the corresponding signal pattern to high order side bits of the image data and outputting the image data to said horizontal driving circuit,
• said modulation circuit including:
• a low order side addition circuit for adding, to P low order side bits of the high order side bits, a logic value of the corresponding signal pattern in response to a logic value of the low order side bit or bits relating to the display of the pseudo gradation;
• a high order side addition circuit for calculating a result of addition of Q high order side bits of the high order side bits except the P lower order side bits when a carry appears at the highest order bit of said low order side addition circuit;
• and
• a selection circuit for selectively outputting the result of addition by said high order side addition circuit or the Q high order side bits in response to the carry, wherein
• said modulation circuit outputs the image data which depend upon the addition result by said low order side addition circuit and the result of the selection of said selection circuit to said horizontal driving circuit.