Dual-gate transistor display

A dual-gate thin-film transistor (DG-TFT) voltage storage matrix, the matrix comprising:

• a first plurality of data lines;
• a second plurality of gate lines;
• a second plurality of bias lines, each bias line being associated with a corresponding gate line;
• and,
• a third plurality of DG-TFT voltage storage circuits, with a unique circuit intervening between each data line and each gate line, each circuit comprising:
• a voltage storage element having an input, and an output;
• and,
• a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a gate line, a second S/D region connected to the voltage storage element input, and a bottom gate connected to a bias line.

A method for controlling a dual-gate thin-film transistor (DG-TFT) voltage storage circuit, the method comprising:

• supplying a circuit with a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line;
• supplying an OFF voltage to the gate line;
• in response to the OFF voltage, disabling current through the DG-TFT to the voltage storage element;
• supplying a first bias voltage to the bias line;
• and,
• decreasing the leakage current through the DG-TFT in response to the first bias voltage.