Semiconductor integrated circuit
OwnerTadahiro Shimizuinventor
Life of this patent
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Abstract
To provide a semiconductor integrated circuit capable of adjusting the skew between gated circuits at a small number of man-hours and with low power consumption. The output terminal of each of gated elements is coupled with the input terminal of at least one circuit element. A delay element is inserted between each of the gated elements and each of the circuit elements to reduce the skew among the corresponding circuits. In this configuration, where an enable signal is supplied to the gate element and no signal is propagated to the circuit following the gated element in a gated circuit, power consumption can be reduced without the delay element.
Claims9
A semiconductor integrated circuit, comprising:
- a clock generator, generating a clock signal;
- a plurality of clock wirings, supplying the clock signal created by the clock generator;
- at least one clock gating circuit, provided so as to correspond to at least a part of the plurality of clock wirings for determining whether or not the clock signal is outputted on the basis of a clock gating signal;
- and
- at least one delay adjusting circuit, provided so as to correspond to at least a part of the plurality of clock wirings for executing delay adjustment for the clock signal outputted from the clock gating circuit.
Dependencies are inferred from the claim text.