Method and apparatus for frequency synthesis

A digital-to-phase converter (DPC) comprising:

• a frequency source for providing a clock signal having a first frequency;
• at least a first delay-locked loop configured to receive the clock signal for generating a first plurality of phase-shifted clock signals, each phase-shifted clock signal having substantially the first frequency and being shifted in phase with respect to the clock signal and with respect to the other phase-shifted clock signals in the first plurality;
• a control device coupled to the frequency source and configured for receiving an input signal identifying a desired frequency for a synthesized signal;
• at least a first selection circuit for receiving the first plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the control device, at least one sequence of the phase-shifted clock signals in the first plurality and outputting a corresponding coarse synthesized signal based on each sequence;
• at least a first variable delay cell having a first input coupled to the selection circuit to receive the corresponding coarse synthesized signal and a second input coupled to the control device, wherein the control device further generates at least one fine tune adjustment signal used by the at least a first variable delay cell to modify the corresponding coarse synthesized signal to generate at an output of the at least a first variable delay cell at least a first fine synthesized signal;
• and
• training apparatus coupled to the at least a first variable delay cell and to the control device for generating at least one set of calibration values for use by the control device to generate the at least one fine tune adjustment signal, the training apparatus comprising:
• a second delay-locked loop having a second number of delay cells and configured to receive the clock signal for generating a second plurality of phase-shifted clock signals, each phase-shifted clock signal having substantially the first frequency and being shifted in phase with respect to the clock signal and with respect to the other phase-shifted clock signals in the second plurality;
• a second selection circuit for receiving the second plurality of phase-shifted clock signals and outputting, under the control of the control device, a calibration signal at an output of the second selection circuit;
• and
• a phase detector coupled to the output of the at least a first variable delay cell and to the output of the second selection circuit for providing at least one phase error signal to the control device for use in generating the at least one set of calibration values.

A method for generating a synthesized signal, comprising the steps of:

• receiving a clock signal having a first frequency;
• receiving an input signal identifying a desired frequency for a synthesized signal;
• generating at least one coarse selection signal for causing at least one sequence of phase-shifted clock signals to be selected, from a first plurality of phase-shifted clock signals, each phase-shifted clock signal having substantially the first frequency and being shifted in phase with respect to the clock signal and with respect to the other phase-shifted clock signals in the first plurality, and for further causing at least one coarse synthesized signal to be output based on the at least one sequence;
• and
• generating at least a first fine adjustment signal for causing the at least one coarse synthesized signal to be modified to generate at least a first fine synthesized signal.