Level shift circuit having timing adjustment circuit for maintaining duty ratio

A level shift circuit for shifting levels of a pair of binary input signals complementary to each other having a first voltage range to produce a pair of binary output signals complementary to each other having a second voltage range, comprising:

• a first level shift circuit unit configured to shift a level of a first one of the binary input signals thereby to produce a first level-shifted signal having the second voltage range;
• a second level shift circuit unit configured to shift a level of a second one of the binary input signals thereby to produce a second level-shifted signal having the second voltage range, one of the first and second level shift circuit units starting level shift operation when another one of the first and second level shift circuit units stops level shift operation;
• and
• a timing adjustment circuit unit configured to produce the binary output signals having the second voltage range by adjusting a pulse width thereof in response to the first level-shifted signal and the second level-shifted signal such that the pulse width is equal to a time interval from when one of the first and second level shift circuit units stops level shift operation to when another one of the first and second level shift circuit units stops level shift operation.