Impedance compensation for I/O buffers

An apparatus comprising,

• an impedance measurement circuit including:
• a voltage divider coupled to a first reference, the voltage divider including:
• a reference impedance circuit;
• and
• an adjustable impedance circuit coupled to the reference impedance circuit at a first node, the adjustable impedance circuit having inputs to adjust the impedance according to a weighted coding scheme;
• a counter including at least one input to cause the counter to count in accordance with the weighted coding scheme and including weighted code outputs coupled to the inputs of the adjustable impedance circuit, wherein at least a portion of the weighted coding scheme includes a pseudo-thermometer code;
• and
• a comparison circuit coupled to the first node to cause the counter to count in accordance with a comparison between the first node and a second reference to obtain an impedance code value when the counter reaches a steady state;
• and
• at least one I/O buffer circuit including:
• a storage circuit to store the impedance code value;
• and
• an adjustable impedance circuit coupled to the storage circuit, wherein a stored impedance code value determines an I/O buffer impedance value.

A system comprising,

• a memory circuit, the memory circuit including a static random access memory (SRAM);
• and a microprocessor including:
• an impedance measurement circuit including:
• a voltage divider coupled to a first reference, the divider comprising a reference impedance and an adjustable impedance circuit, the impedance of the adjustable circuit changeable according to a weighted coding pattern;
• a counter having outputs coupled to inputs of the adjustable impedance circuit, the counter outputs changing in accordance with a weighted coding pattern that includes a pseudo-thermometer code;
• and
• a comparison circuit coupled to cause the counter to count in accordance with an outcome of a comparison between a divider output and a second reference to obtain an impedance code value;
• and
• at least one I/O buffer circuit including a storage circuit coupled to an adjustable impedance circuit, wherein an impedance code value stored in the storage circuit determines an I/O buffer impedance value.

A method comprising:

• applying a first reference voltage to a voltage divider comprising a reference impedance and an adjustable impedance;
• changing the adjustable impedance by selectively activating transistors according to a weighted code until the voltage across the adjustable impedance matches a second reference voltage to obtain a code value, the weighted code including a pseudo-thermometer code;
• and
• compensating at least one I/O buffer by using the code value to set an impedance of the at least one I/O buffer.