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US 2006/0066329 A1Published application
Method and apparatus for providing PCB layout for probe card
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsu Cheng
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsu Cheng
Estimating the term…
An effective and easy to fabricate method to test multiple integrated circuit device designs using a single, probe card design is provided. A universal, probe card design is disclosed herein to test a plurality of integrated circuit devices at the wafer level. Integrated circuit probe pads and probe card probe I/O pins are designed in grid-like pattern on a region of the substrate. Ground terminal encircles the region of the I/O pins and power terminals are provided on the substrate. The I/O terminals can have a constant pitch array or a varying pitch array. The probe card can be used for a family of integrated circuit devices. A method to test flip chip, integrated circuits using a universal probe card has also been disclosed to reduce probe card proliferation and fabrication cost.
In a multi-layer vertical probe card for use in a vertical probe card having a printed circuit board and a plurality of signal channels including at least one ground terminal, a plurality of I/O terminals and a plurality of power terminals, the improvement comprising a first region including the plurality of I/O terminals, a second region containing a ground terminal at least partially surrounding the first region and a third region at least partially surrounding the second region, the third region containing the plurality of power terminals.
A printed circuit board for use with a probe card, the printed circuit board comprising:
A method for fabricated a probe card assembly comprising:
In a multi-layer probe card for use in a vertical probe card having a printed circuit board and a plurality of signal channels including at least one ground terminal, a plurality of I/O terminals and a plurality of power terminals, the improvement comprising providing a region of I/O terminals configured to be universally compatible with the MLC layout configuration.
Dependencies are inferred from the claim text.