Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process
AssigneeAgere Systems Inc.
InventorsMark Bachman, Daniel Chesire, Taeho Kook, Sailesh Merchant
Life of this patent
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AssigneeAgere Systems Inc.
InventorsMark Bachman, Daniel Chesire, Taeho Kook, Sailesh Merchant
Estimating the term…
An interface assembly (20) and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad (24) having a region (28) for performing the bumping process. A test pad (22) is integrally constructed with the bonding pad and includes a probe region (26) for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.
An interface assembly for a semiconductor wafer, said interface assembly comprising:
A method for testing a semiconductor wafer prior to performing a flip chip bumping process, said method comprising:
Dependencies are inferred from the claim text.