Technique for measurement of programmable termination resistor networks on rapidchip and ASIC devices

Abstract

A measurement technique which allows the error components of the testing process to be eliminated by performing a differential-style measurement of the programmable termination resistor network. Since for any given DUT pin which is to be tested, there are multiple possible resistances to be measured, the test process provides that two or more resistance measurements are taken on the same pin. Once those values containing the error components are obtained, they are compared to generate a differential resistance measurement which contains only the actual on-chip DUT resistance with the error components completely removed. The differential value can then be tested against previously defined test limits that are set to guarantee the conformance of the on-chip resistance to the processing specifications. The technique can be applied at either the wafer sort or package test phase of device testing, with the different error components associated with either phase being eliminated.

Dependencies are inferred from the claim text.