Multi-doped semiconductor e-fuse
AssigneeTexas Instruments Incorporated
InventorsFreidoon Mehrad, Richard Rouse, Robert Churchill
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Abstract
The present invention provides a multi-doped semiconductor e-fuse for use in an integrated circuit and a method of manufacture therefore. In one aspect, the semiconductor e-fuse 200 includes a semiconductor body 205 having a neck region 220 interposed a first portion 210 of the semiconductor body 205 and a second portion 215 of the semiconductor body 205. The semiconductor body 205 is doped with opposite type dopants, and a conductive layer 230 is located over and extends across the neck region 220 to electrically connect the first portion 210 with the second portion 215.
Claims30
A multi-doped semiconductor e-fuse for use in an integrated circuit, comprising:
- a semiconductor body having a neck region interposed a first portion and a second portion of the semiconductor body, the semiconductor body being doped with opposite type dopants;
- and
- a conductive layer located over and extending across the neck region that electrically connects the first portion with the second portion.
The multi-doped semiconductor e-fuse as recited in claim 9 wherein the semiconductor body is polysilicon and the silicide layer is a cobalt silicide layer, a titanium silicide layer, or nickel silicide layer.
A method for manufacturing a multi-doped semiconductor e-fuse for use in an integrated circuit, comprising:
- forming a semiconductor body having a neck region interposed a first portion of the semiconductor body and a second portion of the semiconductor body;
- doping the semiconductor body with opposite type dopants;
- and
- forming a conductive layer over and extending across the neck region that electrically connects the first portion with the second portion.
An integrated circuit, comprising:
- transistors;
- a memory interface;
- main memory arrays associated with the transistors and the memory interface;
- redundant memory arrays associated with the memory interface;
- a semiconductor e-fuse, including:
- a semiconductor body having a neck region interposed a first portion of the semiconductor body and a second portion of the semiconductor body, the semiconductor body being doped with opposite type dopants;
- and
- a conductive layer located over and extending across the neck region that electrically connects the first portion with the second portion, the semiconductor e-fuse forming an electrical connection between the main memory arrays and the memory interface;
- interlevel dielectric layers located over the transistors;
- and
- interconnects located within the interlevel dielectric layers and contacting the transistors, the main memory arrays and the redundant memory arrays and the semiconductor e-fuse to form an operational integrated circuit.
Dependencies are inferred from the claim text.