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US 2006/0065935 A1Published application
Patterned backside stress engineering for transistor performance optimization
AssigneeIntel Corporation
InventorsGilroy Vandentop, Rajashree Baskaran
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Abstract
Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.
Claims18
1-20. (canceled)
A method comprising:
- forming a pattern over a first surface of a substrate, the substrate having a first transistor type region and a second transistor type region on a second surface, the pattern covering at least a portion of the first surface opposite the second transistor type region and exposing at least a portion of the first surface opposite the first transistor type region;
- and
- inducing a back side stress in the at least one first transistor type region.
A method comprising:
- selectively inducing stress to the back side of a first transistor type region of a substrate having the first transistor type region and a second transistor type region.
Dependencies are inferred from the claim text.