ESD protection circuit with floating diffusion regions
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Hung Chu, Shao-Chang Huang, Ming-Hsiang Song
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Abstract
This invention discloses an electrostatic discharge (ESD) protection circuit that comprises a substrate of a predetermined type, at least one MOS transistor being coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD event, a substrate contact region, and at least one floating diffusion region formed in a substrate area between the MOS transistor and the substrate contact region for reducing a trigger-on voltage of the MOS transistor during the ESD event.
Claims25
An electrostatic discharge (ESD) protection circuit comprising:
- at least one MOS transistor coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD event;
- a substrate having a contact area;
- at least one floating diffusion region formed in the substrate between the MOS transistor and the substrate contact region;
- a first isolation structure and a second isolation structure placed between the MOS transistor and the substrate contact region wherein said at least one floating diffusion region is between said first isolation structure and said second isolation structure.
2-3. (canceled)
An electrostatic discharge (ESD) protection circuit comprising:
- a guard ring forming a substrate contact region in the substrate;
- at least one MOS transistor coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD event;
- at least one floating diffusion region formed in the substrate between the MOS transistor and the substrate contact region;
- a first isolation structure and a second isolation structure placed between the MOS transistor and the substrate contact region wherein said at least one floating diffusion region is between said first isolation structure and said second isolation structure.
(canceled)
An electrostatic discharge (ESD) protection circuit comprising:
- a substrate having a contact area;
- at least one MOS transistor being coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD event;
- at least one floating diffusion region formed in the substrate between the MOS transistor and the substrate contact region and coupled to at least one capacitance device;
- a first isolation structure and a second isolation structure placed between the MOS transistor and the substrate contact region wherein said at least one floating diffusion region is between said first isolation structure and said second isolation structure.
22-23. (canceled)
An electrostatic discharge (ESD) protection circuit comprising:
- at least one MOS transistor coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD event;
- a first diffusion region directly connected to the MOS transistor for dissipating the ESD current from the pad;
- a second diffusion region connected to the first diffusion region for dissipating the ESD from the pad;
- an isolation structure interposed between the first diffusion region and the second diffusion region;
- wherein the second diffusion region does not directly contact a diffusion region of the MOS transistor.
Dependencies are inferred from the claim text.