ESD protection for high voltage applications

An apparatus, comprising:

• a first N doped region located in a P doped substrate;
• a first P doped region located in the first N doped region;
• a first P+ doped region located in the first P doped region and substantially surrounded on all sides within the substrate by the first P doped region;
• a second N doped region located in the first N doped region and substantially surrounding the first P doped region, the second N doped region and the first P doped region having substantially similar depths;
• a first N+ doped region located in the second N doped region and substantially surrounded on all sides within the substrate by the second N doped region;
• a second P doped region located in the substrate adjacent the first N doped region;
• a second N+ doped region located in the second P doped region and substantially surrounded on all sides within the substrate by the second P doped region;
• a third N doped region located in the substrate adjacent the second P doped region;
• a third N+ doped region located in the third N doped region and substantially surrounded on all sides within the substrate by the third N doped region;
• a third P doped region located in the substrate adjacent the third N doped region;
• a fourth N+ doped region located in the third P doped region and substantially surrounded on all sides within the substrate by the third P doped region;
• a second P+ doped region located in the second and third P doped regions and the third N doped region and substantially surrounding the second, third, and fourth N+ doped regions;
• and
• an electrode located over the substrate and laterally interposing the third and fourth N+ doped regions, the electrode laterally extending from between the third and fourth N+ doped regions at least to at least one of the third and fourth N+ doped regions.

A method of manufacturing an apparatus, comprising:

• forming a first N doped region to a first depth in a P doped substrate;
• forming a first P doped region to a second depth within the first N doped region, wherein the second depth is substantially less than the first depth;
• forming a first P+ doped region to a third depth within the first P doped region, wherein the third depth is substantially less than the second depth;
• forming a second N doped region to the second depth within the first N doped region and substantially laterally surrounding the first P doped region;
• forming a first N+ doped region to the third depth in an annulus shape within the second N doped region;
• forming a second P doped region to the second depth within the substrate and adjacent the second N doped region;
• forming a second N+ doped region to the third depth within the second P doped region;
• forming a third N doped region to the second depth within the substrate and adjacent the second P doped region;
• forming a third N+ doped region to the third depth within the third N doped region;
• forming a third P doped region to the second depth within the substrate and adjacent the third N doped region;
• forming a fourth N+ doped region to the third depth within the third P doped region;
• and
• forming an electrode over the substrate and extending at least between the third and fourth N+ doped regions.

An apparatus comprising:

• an electrostatic discharge (ESD) protected device;
• and
• a protection device coupled to the ESD protected device and including:
• a diode located in a substrate;
• and
• a metal oxide semiconductor (MOS) device located in the substrate adjacent the diode, wherein both the diode and the MOS device are coupled to an input device, and an ESD protection device is formed by at least a portion of the diode and at least a portion of the MOS device, collectively, wherein the diode and the MOS device each have an operating voltage of at least about 12 volts.

An apparatus, comprising:

• an electrostatic discharge (ESD) protected device;
• and
• a protection device coupled to the ESD protected device and including:
• a P-type metal oxide semiconductor (PMOS) device located in a substrate;
• and
• an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein a first P doped region in the PMOS device and a first N doped region in the NMOS device are coupled to an input device, and an ESD protection device is formed by at least a portion of the PMOS device and at least a portion of the NMOS device, collectively.