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US 2006/0053400 A1Published application
Method for correcting layout errors
AssigneeInfineon Technologies AG
InventorsDirk Meyer, Uwe Mueller
Life of this patent
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AssigneeInfineon Technologies AG
InventorsDirk Meyer, Uwe Mueller
Estimating the term…
A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least possible complexity, the layout (10) is examined for the presence of layout errors (20, 30) with the aid of predetermined design rules, identical layout errors (20, 30) are combined in a respective error class, and all layout errors (30) of an error class that are still present are automatically corrected without further checking in an identical manner as soon as the correction of a layout error (20) of the respective error class that is used as an error representative has been performed.
A method for eliminating layout errors of a layout, the method comprising:
A data processing system for eliminating layout errors of a layout, the data processing system comprising a microprocessor device, which is embodied in such a way that it examines the layout for the presence of layout errors with the aid of predetermined design rules;
Dependencies are inferred from the claim text.