Memory devices with error detection using read/write comparisons
AssigneeSamsung Electronics Co., Ltd.
InventorHyung-Gon Kim
Life of this patent
Estimating the term…
Abstract
A memory device includes a main memory cell array and a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array. The device further includes a parity generator configured to generate a second parity code responsive to reading of the stored data from the main memory cell array, and a comparator configured to compare the first and second parity codes. The parity generator may be configured to generate the second parity code during a copyback operation.
Claims24
A memory device comprising:
- a main memory cell array;
- a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array;
- a parity generator configured to generate a second parity code responsive to reading of the stored data from the main memory cell array;
- and
- a comparator configured to compare the first and second parity codes.
The memory device of claim.7, wherein the selecting means comprises a fuse circuit.
A memory device comprising:
- a memory cell array;
- a first parity generator configured to generate a first parity code responsive to input of data to the memory cell array;
- a second parity generator configured to generate a second parity code responsive to output of data from the memory cell array;
- and
- a comparator configured to compare the first and second parity codes.
A method for detecting errors in a memory device, comprising:
- generating a first parity code responsive to input of data to a memory cell array;
- generating a second parity code responsive to output of the data from the memory cell array;
- and
- comparing the first and second parity codes to detect an error.
Dependencies are inferred from the claim text.