Integrated circuit yield and quality analysis methods and systems

A computer-implemented method, comprising:

• receiving a representation of an integrated circuit layout;
• receiving one or more recommended design parameters for manufacturing an integrated circuit;
• and
• determining extraction rules from one or more of the recommended design parameters, the extraction rules comprising rules for identifying two or more sets of defect candidates from the representation of the integrated circuit layout.

A computer-implemented method, comprising:

• determining a modified set of design manufacturing rules for evaluating the presence of potential defects in manufactured integrated circuits, the act of determining a modified set of design manufacturing rules comprising deriving the modified set of design manufacturing rules at least in part from a first set of design manufacturing rules, the first set of design manufacturing rules defining plural classes of types of potential defects, including at least first and second classes of defect types, the modified set of design manufacturing rules defining at least a first set of a first subclass of plural design manufacturing rules associated with the first class of design manufacturing rules and a second set of a second subclass of plural design manufacturing rules associated with the second class of design manufacturing rules;
• ranking at least a plurality of the first and second subclasses of design manufacturing rules by the likelihood of such ranked first and second subclasses of design manufacturing rules identifying defects in the manufactured integrated circuits;
• and
• extracting potential defects from a physical layout description of the integrated circuit that satisfy the first and second subclasses of design manufacturing rules.