Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
AssigneeMicron Technology, Inc.
InventorsMichael Connell, Tongbi Jiang
Life of this patent
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Abstract
A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach and be of a markable material for an enhanced marking method.
Claims24
A manufacturing method for a wafer comprising:
- reducing a cross-section of the wafer by thinning material from the back side of the wafer;
- applying a stress-balancing layer to the wafer substantially balancing the stress caused by a layer of material on the other side of the wafer;
- and singulating the wafer into at least one semiconductor die.
A method in accordance with claim 9, wherein said selected portion comprises a majority of said thinned semiconductor die.
A stress compensation method comprising:
- reducing a cross-section of a wafer by thinning the back side thereof;
- applying a rigid stress-balancing layer to a portion of the thinned back side comprising a material for marking with indicia;
- exposing a portion of the material to optical energy using one of a Nd:YAG (yttrium aluminum garnet), Nd:YLP (pulsed yttrium fiber laser) and carbon dioxide laser;
- and singulating said wafer into at least one semiconductor die.
A method for offsetting forces acting on a wafer comprising:
- reducing a cross-section of the wafer by thinning material from the back side of the wafer;
- applying a stress-balancing layer to the wafer substantially balancing the stress caused by a layer of material on the other side of the wafer;
- and
- singulating the wafer into at least one semiconductor die.
A force balancing method comprising:
- reducing a cross-section of a wafer by thinning the back side thereof;
- applying a rigid stress-balancing layer to a portion of the thinned back side comprising a material for marking with indicia;
- exposing a portion of the material to optical energy using one of a Nd:YAG (yttrium aluminum garnet), Nd:YLP (pulsed yttrium fiber laser) or carbon dioxide laser;
- and
- singulating said wafer into at least one semiconductor die.
A planarization method for a semiconductor die comprising:
- reducing a cross-section of the wafer by thinning material from the back side of the wafer;
- applying a stress-balancing layer to the wafer substantially balancing the stress caused by a layer of material on the other side of the wafer;
- and
- singulating the wafer into at least one semiconductor die.
Dependencies are inferred from the claim text.