Pll using unbalanced quadricorrelator
AssigneeKoninklijke Philips Electronics N.V.
InventorMihai Sanduleanu
Life of this patent
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Abstract
A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, {overscore (PQ)} provided by the first multiplexer (31) and by a second signal pair (PI, {overscore (PI)}) provided by the second multiplexer (32).
Claims7
A Phase Locked Loop comprising a frequency detector including an unbalanced quadricorrelator, the quadricorrelator comprising a frequency detector including double edge clocked bi-stable circuits coupled to a first multiplexer and to a second multiplexer being controlled by a signal having a same bitrate as the incoming signal, and a phase detector controlled by a first signal pair provided by the first multiplexer and by a second signal pair provided by the second multiplexer.
A Phase Locked Loop as claimed in 5, wherein the error signal is inputted to a coarse control input of the voltage controlled oscillator via a first charge pump coupled to a first low-pass filter coupled to an adder.
Dependencies are inferred from the claim text.