Address coding method and address decoder for reducing sensing noise during refresh operation of memory device
AssigneeSamsung Electronics Co., Ltd.
InventorChul-Woo Park
Life of this patent
Estimating the term…
Abstract
An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, includes: activating adjacent banks shared by at least two memory blocks during a refresh operation of the memory device, and enabling the refresh operation in each bank alternately between the at least two memory blocks. The method includes activating adjacent banks shared by the at least two memory blocks during another operation of the memory device, and enabling the another operation in each bank alternately between the at least two memory blocks.
Claims12
An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, comprising:
- activating adjacent banks shared by the at least two memory blocks during a refresh operation of the memory device;
- enabling the refresh operation in each bank alternately between the at least two memory blocks;
- activating the adjacent banks shared by the at least two memory blocks during another operation of the memory device;
- and
- enabling the another operation in each bank to one of the at least two memory blocks.
A memory device including a plurality of banks each being shared by a plurality of upper memory blocks and a plurality of lower memory blocks, comprising:
- coding address signals of adjacent banks for alternately activating the adjacent banks of the upper memory blocks and the lower memory blocks, during a refresh operation of the memory device;
- and
- coding address signals of adjacent banks for activating the adjacent banks of one of the upper memory blocks and the lower memory blocks, during another operation of the memory device.
An address decoder of a memory device having a structure in which a plurality of banks are shared by an upper memory block and a lower memory block, the address decoder comprising:
- a plurality of multiplex units, each multiplex unit selecting one of an internal address signal and an external address signal, the plurality of multiplex units for allocating each of the plurality of banks to one of the upper memory block and the lower memory block, in response to a refresh signal;
- and
- a plurality of bank decoders, each bank decoder connected to each of the plurality of banks, receiving the internal address signal or the external address signal output from the multiplex units with row address signals input to the memory device, decoding the received signals, and activating word lines in corresponding banks,
- wherein during a refresh operation of the memory device, the multiplex units provide the internal address signal and an inverted signal of the internal address signal alternately to the bank decoders.
Dependencies are inferred from the claim text.