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US 2006/0050569 A1Published application
Semiconductor memory apparatus and activation signal generation method for sense amplifier
AssigneeFujitsu Limited
InventorHiroshi Shimizu
Life of this patent
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Abstract
A semiconductor memory apparatus, comprising a cell array comprising a plurality of memory cells; a sense amplifier; and a self-timing unit comprising a plurality of dummy bit-lines, selecting the dummy bit-line based on the position of the memory cell of which a data is read out, and generating an activation signal for controlling an activation timing of a sense amplifier at a time of reading data.
Claims13
A semiconductor memory apparatus, comprising:
- a cell array comprising a plurality of memory cells;
- a sense amplifier;
- and
- a self-timing unit comprising a plurality of dummy bit-lines, selecting said dummy bit-line based on a position of said memory cell of which a data is read out and generating an activation signal for controlling an activation timing of the sense amplifier at a time of reading data.
1 more element
A generation method for an activation signal controlling an activation timing of a sense amplifier amplifying a signal read out of a memory cell in a semiconductor memory apparatus,
- comprising a plurality of dummy bit-lines;
- selecting said dummy bit-line from among said plurality of dummy bit-lines based on a position of said data read-out memory cell at a time of reading data;
- and
- generating said activation signal based on a signal of said selected dummy bit-line.
1 more element
Dependencies are inferred from the claim text.