Resistive memory arrangement
AssigneeInfineon Technologies AG
InventorsCorvin Liaw, Thomas Roehr, Michael Kund
Life of this patent
Estimating the term…
Abstract
Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.
Claims16
A resistive memory arrangement having a cell array structured in rows and columns, comprising:
- resistive memory cells connected to a drive element for driving;
- each drive element jointly being connected to n cell resistors forming a memory cell;
- wherein control electrodes of the drive elements of a column are jointly connected to a word line running in the column direction;
- wherein first controlled electrodes of the drive elements of a row are jointly connected to a bit line running in the row direction;
- wherein second controlled electrodes of each drive element are in each case connected to the first electrodes of the n cell resistors;
- and
- wherein the second electrodes of the n cell resistors of each column are individually connected in each case to a plate line running in the column direction.
A method for writing to a CBRAM resistance element of a resistive memory arrangement having a cell array structured in rows and columns with resistive memory cells connected to a drive element, each drive element jointly being connected to a plurality of CBRAM resistive elements forming a memory cell, the method comprising:
- opening a word line of a corresponding memory cell;
- placing all plate lines and bit lines of unselected resistance elements at a specific plate potential;
- increasing the plate line voltage of a selected resistance element by a specific write voltage ΔVwrite of approximately 150 mV to VPL+ΔVwrite;
- and
- decreasing the voltage of an associated bit line by the write voltage ΔVwrite to VPL−ΔVwrite.
A method for reading a CBRAM resistance element of a resistive memory arrangement having a cell array structured in rows and columns with resistive memory cells connected to a drive element, each drive element jointly being connected to a plurality of CBRAM resistive elements forming a memory cell, the method comprising:
- opening a word line of a corresponding memory cell;
- holding the bit line voltage of a selected memory cell at a specific plate potential;
- placing the voltage on the plate line of the resistance element to be read at a specific read voltage Vread lying approximately 100 mV above the plate potential;
- holding all plate lines and bit lines of nonselected resistance elements at plate potential;
- and
- detecting a sense current flowing through the resistance element in accordance with the programming state thereof.
A method for erasing a CBRAM resistance element of a resistive memory arrangement having a cell array structured in rows and columns with resistive memory cells connected to a drive element, each drive element jointly being connected to a plurality of CBRAM resistive elements forming a memory cell, the method comprising:
- opening the word line corresponding to the memory cell with the resistance element to be erased;
- placing all plate lines and bit lines of unselected resistance elements at a specific plate potential;
- reducing the plate line voltage of the selected resistance element by a specific erase voltage ΔVerase to VPL−ΔVerase;
- and
- increasing the voltage of the associated bit line by the erase voltage ΔVerase to VPL+ΔVerase.
A method for operating a resistive memory arrangement having a cell array structured in rows and columns with resistive memory cells connected to a drive element, each drive element jointly being connected to a plurality of CBRAM resistive elements forming a memory cell, the method comprising:
- activating a word line of a column;
- driving the plate lines of this column which are connected to the cell resistors of the resistive memory cells successively by means of a counter, in that, during the reading process, the information of the successively driven cell resistors of the memory cells of this column is read out via the bit lines and buffer-stored in a buffer register and output as an entire page;
- and
- during the writing process, externally arriving write data of a page are buffer-stored in the buffer register, the corresponding word line of a column is activated and the write data buffer-stored in the buffer register are written sequentially, beginning with the first plate line up to the last plate line, to the cell resistors of the memory cells of this column.
A method for parallel erasure of all resistance elements connected to a drive element along a word line in a resistive memory arrangement having a cell array structured in rows and columns with resistive memory cells connected to a drive element, each drive element jointly being connected to a plurality of CBRAM resistive elements forming a memory cell, the method comprising:
- opening the word lines corresponding to the memory cells with the resistance elements to be erased;
- placing all plate lines and bit lines of unselected resistance elements at a specific plate potential;
- holding the voltages on the plate lines of the selected cells at the plate line potential;
- and
- increasing the voltage on the corresponding bit lines by a specific erase voltage ΔVerase.
Dependencies are inferred from the claim text.