Memory circuit having memory cells which have a resistance memory element

A method for accessing a plurality of memory cells connected in series between a first ground line and a second ground line, wherein each of the plurality of memory cells comprises a resistance memory element and a driver transistor attached in parallel across an anode and a cathode of the resistance memory element, the method comprising:

• receiving an address of a memory cell in the plurality of memory cells;
• lowering a signal applied to the driver transistor attached to the memory cell and asserting a signal applied to other memory cells in the plurality of memory cells, thereby creating a current path through the resistance memory element of the memory cell;
• if the address is an even address, connecting a first end of the series of memory cells to the first ground line and connecting a second end of the series of memory cells to a bitline;
• and
• if the address is an odd address, connecting the second end of the series of memory cells to the second ground line and connecting the first end of the series of memory cells to the bitline.

A memory device comprising:

• a plurality of memory cells connected in series between a first ground line and a second ground line, wherein each of the plurality of memory cells comprises:
• a resistance memory element;
• and
• a driver transistor attached in parallel across an anode and a cathode of the resistance memory element;
• a decoder configured to:
• receive an address of a memory cell in the plurality of memory cells;
• lower a signal applied to the driver transistor of the memory cell and assert a signal applied to other memory cells in the plurality of memory cells, thereby creating a current path through the resistance memory element of the memory cell;
• if the address is an even address, connect a first end of the plurality of memory cells connected in series to the first ground line and connect a second end of the plurality of memory cells connected in series to a bitline;
• and
• if the address is an odd address, connect the second end of the plurality of memory cells connected in series to the second ground line and connect the first end of the plurality of memory cells connected in series to the bitline.

A memory device comprising:

• a plurality of means for storing connected in series between a first ground line and a second ground line, wherein each of the plurality of means for storing comprises:
• a memory element;
• and
• means for driving attached in parallel across an anode and a cathode of the memory element;
• means for controlling configured to:
• receive an address of one of the means for storing in the plurality of means for storing;
• lower a signal applied to the means for driving for the one of the means for storing and assert a signal applied to other means for storing in the plurality of means for storing, thereby creating a current path through the memory element of the means for storing;
• if the address is an even address, connect a first end of the plurality of means for storing to the first ground line and connect a second end of the plurality of means for storing to a bitline;
• and
• if the address is an odd address, connect the second end of the plurality of means for storing connected in series to the second ground line and connect the first end of the plurality of means for storing connected in series to the bitline.

A memory device comprising:

• a plurality of memory cells connected in series between a first ground line and a second ground line, wherein each of the plurality of memory cells comprises:
• a resistance memory element;
• a driver transistor attached in parallel across an anode and a cathode of the resistance memory element;
• and
• wherein one of the anode and the cathode are attached to a corresponding one of an anode or a cathode of an adjacent memory cell;
• a decoder configured to:
• if an address applied to the decoder circuit is an even address, connect a first end of the plurality of memory cells connected in series to the first ground line and connect a second end of the plurality of memory cells connected in series to a bitline;
• and
• if the address applied to the decoder circuit is an odd address, connect the second end of the plurality of memory cells connected in series to the second ground line and connect the first end of the plurality of memory cells connected in series to the bitline.