Code driver for a memory controller

A memory controller comprising:

• a parallel interface for transmitting instructions, the parallel interface comprising a plurality of transmission paths, each transmission path corresponding to a bit of an instruction;
• control circuitry configured to transmit an instruction by:
• determining whether bits of the instruction are used to process the instruction by a receiver of the instruction;
• and
• for each bit used to process the instruction, activating a respective transmission path corresponding to the bit used to process the instruction without activating respective transmission paths corresponding to those bits not used to process the instruction thereby driving only those bits used to process the instruction across the respective transmission paths.

A memory controller comprising:

• means for parallel interfacing configured to transmit instructions, the means for parallel interfacing comprising a plurality of means for transmitting, each means for transmitting corresponding to a bit of an instruction;
• means for controlling configured to transmit an instruction by:
• determining whether bits of the instruction are used to process the instruction by a receiver of the instruction;
• and
• for each bit used to process the instruction, activating a respective means for transmitting corresponding to the bit used to process the instruction without activating respective transmission paths corresponding to those bits not used to process the instruction thereby driving only those bits used to process the instruction across the respective means for transmitting.

A memory controller comprising:

• instruction circuitry configured to generate an instruction;
• parallel transmission circuitry configured to transmit bits of the instruction, wherein each bit of the instruction is transmitted across a respective transmission path;
• selection circuitry configured to:
• receive one or more first bits of the instruction;
• based on the one or more first bits of the instruction, determine whether one or more second bits of the instruction are used to process the instruction by a receiver of the instruction;
• generate one more selection signals, wherein the selection signals activate only the respective transmission paths for the one or more second bits of the instruction which are used to process the instruction.