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US 2006/0049863 A1Published application
Clock distributor for use in semiconductor logics for generating clock signals when enabled and a method therefor
AssigneeOki Electric Industry Co., Ltd.
InventorNobuyuki Endo
Life of this patent
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Abstract
A clock distributor circuit is provided which works with power consumption reduced in semiconductor logic circuitry including clock synchronous circuits. The clock distributor circuit includes clock generation circuits generating gated clock signals in response to a clock enable signal to supply clock synchronous circuits with the generated clock signals. It is thus possible to reduce the power that would otherwise consumed by the toggling of the clock signal. A clock distribution method therefor is also provided.
Claims14
A clock distributor circuit comprising:
- at least one clock synchronous circuit for receiving a data signal and output the data signal synchronized with a clock as an output signal;
- and
- at least one clock generating circuit for receiving a clock enable signal and generating, in response to the clock enable signal, a gated clock signal to output the gated clock signal;
- said at least one clock generating circuit being connected to said at least one clock synchronous circuit to supply the gated clock signals substantially simultaneously.
1 more element
A method of distributing a clock, comprising:
- at least one clock synchronous step of receiving a data signal and output the data signal synchronized with a clock as an output signal;
- and
- at least one clock generating step of receiving a clock enable signal and generating, in response to the clock enable signal, a gated clock signal to output the gated clock signal;
- said at least one clock generating step being associated with said at least one clock synchronous step to supply the gated clock signal substantially simultaneously.
1 more element
Dependencies are inferred from the claim text.