Integrated semiconductor memory with clock generation

A method for generating a clock signal for operating an integrated semiconductor device, comprising:

• providing an integrated semiconductor device that is drivable by an external clock signal that assumes an external clock signal level;
• providing the integrated semiconductor device with a first clock circuit having a first sensitivity time and a sensitivity level, wherein the first clock circuit generates an internal clock signal with a first level in response to the external clock signal level lying above the sensitivity level of the first clock circuit for at least the duration of the first sensitivity time, and generates the internal clock signal with a second level in response to the external clock signal level lying below the sensitivity level of the first clock circuit for at least the duration of the first sensitivity time;
• providing the integrated semiconductor memory with a second clock circuit having a sensitivity level and a second sensitivity time that is greater than the first sensitivity time, wherein the second clock circuit generates the internal clock signal with the first level in response to the external clock signal level lying above the sensitivity level of the second clock circuit for at least the duration of the second sensitivity time, and generates the internal clock signal with the second level in response to the external clock signal level lying below the sensitivity level of the second clock circuit for at least the duration of the second sensitivity time;
• activating the first clock circuit to generate the internal clock signal in response to driving the integrated semiconductor device with a first external clock signal;
• and
• activating the second clock circuit to generate the internal clock signal in response to driving the integrated semiconductor device with a second external clock signal that has a lower frequency than the first external clock signal.

A method for generating a clock signal for operating an integrated semiconductor device, comprising:

• providing the integrated semiconductor device with a clock generator circuit comprising a differential amplifier with a controllable current source for generating a current that is fed into the differential amplifier;
• driving the integrated semiconductor device with an external clock signal;
• evaluating the frequency of the external clock signal;
• supplying a first current from the controllable current source to the differential amplifier in response to the frequency of the external clock signal lying above a frequency threshold;
• and
• supplying a second current from the controllable current source to the differential amplifier in response to the frequency of the external clock signal lying below the frequency threshold, wherein the second current is less than the first current.