US 2006/0049528 A1 · Semiconductor chip stack structure and method for forming the same

Abstract

Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of a bonding wire is ball-bonded to the substrate and the other end is stitch-bonded to the metal bump. The second chip is stacked on the first chip. The bonding wire is substantially parallel with a top surface of the first chip. Accordingly, the chip stack structure and method minimize a space between the first chip and the second chip, thereby reducing the total height of semiconductor chip stack.

Claims11

Dependent claims

A method for manufacturing a semiconductor chip stack, the method comprising:

(a) providing a substrate including a die-mounting surface and wiring patterns;
(b) attaching a first chip to the die-mounting surface of the substrate;
(c) forming first conductive bumps on first electrode pads of the first chip;
(d) electrically interconnecting the substrate and the first chip through first bonding wires, wherein expanses of the first bonding wires are substantially parallel with the top surface of the first chip;
(e) stacking a second chip over the first chip using the expanse;
and
(f) electrically interconnecting second electrode pads of the second chip and the wiring patterns of the substrate.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/261,156Filed 27 Oct 2005

Priority

KR 2002-1532921 Mar 2002

Published

9 Mar 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10W 90/00
Package configurations
H10W 72/073
Connecting or disconnecting: of die-attach connectors
H10W 72/07327
Aligning: involving guiding structures, e.g. spacers or supporting members
H10W 72/075
Connecting or disconnecting: of bond wires

Semiconductor chip stack structure and method for forming the same

Life of this patent

Semiconductor chip stack structure and method for forming the same

Life of this patent

Abstract

Claims11