Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory

A non-volatile semiconductor memory having a plurality of memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor comprising:

• source and drain regions having a first conductivity type disposed on an insulating layer;
• a channel region having the first conductivity type disposed between the source and drain regions, and having a lower impurity concentration than the source and drain regions;
• a floating gate electrode disposed above the channel region and insulated from the channel region;
• and
• a control gate electrode disposed above the floating gate electrode and insulated from the floating electrode.

A method for fabricating a non-volatile semiconductor memory comprising, forming a depletion mode memory cell transistor, comprising:

• depositing a gate insulating film on a semiconductor layer having a first conductivity type disposed on an insulating layer;
• depositing a floating gate electrode on the gate insulating film;
• depositing an inter-electrode insulating film on the floating gate electrode;
• depositing a control gate electrode on the inter-electrode insulating film;
• forming a groove penetrating the control gate electrode, the inter-electrode insulating film and the floating gate electrode;
• and
• forming source and drain regions having the first conductivity type in the semiconductor layer under the groove.