Ferroelectric memory arrangement
AssigneeInfineon Technologies AG
InventorsRainer Bruchhaus, Martin Gutsche, Cay-Uwe Pinnow
Life of this patent
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Abstract
A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.
Claims21
A ferroelectric memory arrangement comprising:
- a memory cell comprising:
- a select transistor;
- and
- a ferroelectric storage capacitor coupled to the select transistor, the ferroelectric storage capacitor including vertical electrodes, and a ferroelectric dielectric between the vertical electrodes, configured wherein a dimension of the ferroelectric dielectric in a lateral direction is approximately equal to a crystallite size of the ferroelectric dielectric material such that an in-plane orientation of the crystallites is reduced.
A ferroelectric memory arrangement comprising:
- a plurality of memory cells, each memory cell comprising:
- a vertical ferroelectric storage capacitor that includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, connected to a select transistor, the ferroelectric dielectric comprising a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer, wherein a lateral dimension of the ferroelectric dielectric layers of each ferroelectric storage capacitor is of the order of magnitude of their crystallite size.
A ferroelectric memory arrangement comprising:
- a plurality of memory cells, each memory cell comprising:
- a vertical ferroelectric storage capacitor that includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, connected to a select transistor, the ferroelectric dielectric comprising a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer, wherein a lateral dimension of the ferroelectric dielectric layers of each ferroelectric storage capacitor is of the order of magnitude of their crystallite size, wherein the number of ferroelectric dielectric layers is selected as a function of a thickness of the ferroelectric dielectric layer and crystallite size.
A ferroelectric memory arrangement comprising:
- a memory cell comprising:
- means for providing a select transistor;
- and
- means for providing a ferroelectric storage capacitor coupled to the select transistor, the ferroelectric storage capacitor including vertical electrodes, and a ferroelectric dielectric between the vertical electrodes, configured wherein a dimension of the ferroelectric dielectric in a lateral direction is approximately equal to a crystallite size of the ferroelectric dielectric material such that an in-plane orientation of the crystallites is reduced.
A method of making a ferroelectric memory arrangement comprising:
- providing a select transistor;
- depositing a first insulating layer over the select transistor;
- depositing a first ferroelectric dielectric layer over the first insulation layer;
- crystallizing the first ferroelectric dielectric layer;
- depositing a second insulating layer over the first ferroelectric layer;
- depositing a second ferroelectric dielectric layer over the second insulation layer;
- depositing a third insulating layer over the second ferroelectric layer;
- and
- depositing a third ferroelectric dielectric layer over the third insulation layer.
Dependencies are inferred from the claim text.