Thin film transistor array substrate and fabricating method thereof

A method of fabricating a thin film transistor array substrate, the method comprising:

• forming a gate pattern including a gate line and a gate electrode on a substrate;
• forming a gate insulating film, an amorphous silicon layer and an n+ amorphous silicon layer on the substrate provided with the gate pattern, and forming a source/drain metal layer containing at least one material of tungsten silicide (WSix), cobalt silicide (CoSix) or nickel silicide (NiSix) by PECVD or MOCVD;
• patterning the amorphous silicon layer, the n+ amorphous silicon layer and the source/drain metal layer to provide a semiconductor pattern and a source/drain pattern including the data line, the source electrode and the drain electrode formed on the semiconductor pattern;
• forming a protective film having a contact hole exposing a portion of the drain electrode on the substrate provided with the source/drain pattern;
• and
• forming a pixel electrode connected, via the contact hole, to the drain electrode.

A thin film transistor array substrate, comprising:

• a gate pattern including a gate line, a gate electrode connected to the gate line and a lower gate pad electrode extended from the gate line;
• a gate insulating film provided on the gate pattern;
• a source/drain pattern including a data line intersecting the gate line with the gate insulating film therebetween, the source/drain pattern containing at least one of tungsten silicide (WSix), cobalt silicide (CoSix) or nickel silicide (NiSix), a lower data pad electrode extended from the data line, a source electrode connected to the data line and a drain electrode opposed to the source electrode;
• a thin film transistor provided at each intersection between the gate line and the data line;
• and
• a pixel electrode provided at a pixel area defined by each intersection between the gate line and the data line and connected to the thin film transistor, an upper gate pad electrode connected to the lower gate pad electrode and an upper data pad electrode connected to the lower data pad electrode.

A method of fabricating a thin film transistor array substrate using four mask processes, the method comprising:

• forming a gate pattern including a gate line and a gate electrode on a substrate using a first mask process;
• forming a gate insulating film, an amorphous silicon layer and an n+ amorphous silicon layer on the substrate provided with the gate pattern, and forming a source/drain metal layer within a single piece of equipment;
• patterning the amorphous silicon layer, the n+ amorphous silicon layer and the source/drain metal layer using a second mask process to provide a semiconductor pattern and a source/drain pattern including the data line, the source electrode and the drain electrode formed on the semiconductor pattern;
• forming a protective film having a contact hole exposing a portion of the drain electrode on the substrate provided with the source/drain pattern using a third mask process;
• and
• forming a pixel electrode connected, via the contact hole, to the drain electrode using a fourth mask process.