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US 2006/0044894 A1Published application
Enhanced timing margin memory interface
AssigneeThunder Creative Technologies, Inc.
InventorsRobert Washburn, Robert McClanahan
Life of this patent
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Abstract
The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.
Claims12
A memory interface comprising:
- a first input signal coupled to a first input of an OR gate through a first transition time adjust circuit;
- a second input signal coupled to a second input of an OR gate through a second transition time adjust circuit.
Dependencies are inferred from the claim text.