Methods and apparatus for error correction of transparent GFP (generic framing procedure) superblocks

An apparatus for correcting errors in a GFP-T (generic framing procedure-transparent mode) superblock having 64 bytes of data, a flag byte, and a 16 bit CRC, comprising:

• a data buffer for buffering the 64 bytes of data;
• a flag byte buffer for buffering the flag byte;
• a CRC calculation circuit for calculating the CRC remainder;
• a single bit error syndrome table;
• first comparison logic coupled to said CRC calculation circuit and to said single bit error syndrome table;
• single bit error correction logic coupled to said data buffer, said flag byte buffer, and to said first comparison logic;
• a double bit error syndrome table;
• second comparison logic coupled to said CRC calculation circuit and to said double bit error syndrome table;
• double bit error correction logic coupled to said single bit error correction logic and to said second comparison logic, wherein
• the flag byte is processed first and the data bytes are processed eight bytes at a time.

An apparatus for correcting errors in a GFP-T (generic framing procedure-transparent mode) superblock having 64 bytes of data, a flag byte, and a 16 bit CRC, comprising:

• a data buffer means for buffering the 64 bytes of data;
• a flag byte buffer means for buffering the flag byte;
• a CRC calculation circuit means for calculating the CRC remainder;
• a single bit error syndrome table means for indicating the location of a single bit error;
• first comparison logic means coupled to said CRC calculation circuit means and to said single bit error syndrome table means, said first comparison logic means for determining whether the CRC remainder matches an entry in said single bit error syndrome table means;
• single bit error correction logic means coupled to said data buffer means, said flag byte buffer means, and to said first comparison logic means, said single bit error correction logic means for correcting a single bit error indicated by said first comparison logic means;
• a double bit error syndrome table means for indicating the location of a first error of a double bit error;
• second comparison logic means coupled to said CRC calculation circuit means and to said double bit error syndrome table means, said second comparison logic means for determining whether the CRC remainder matches an entry in said double bit error syndrome table means;
• double bit error correction logic means coupled to said single bit error correction logic means and to said second comparison logic means, said double bit error correction logic means for correcting a double bit error indicated by said second comparison logic means, wherein
• the flag byte is processed first and the data bytes are processed eight bytes at a time.